1. Technical Field
The present invention generally relates to memory accessing schemes. More particularly, the present invention relates to memory bank selection.
2. Background Art
As memory densities, in particular that of dynamic random access memory (DRAM), continue to increase, accessing efficiency becomes more of an issue. High density memory modules may be partitioned into units referred to as "banks". In the past, each bank has required individual select signals, such as row address select (RAS) and column address select (CAS), for accessing. In addition, typically only one bank at any given time may be active. Access efficiency would be increased if the number of select signals needed could be reduced, since the number of select signal inputs or pins would be reduced, and multiple banks could be active simultaneously.
One solution has been to clock a single set of select or enable signals used for any bank together with a bank address. In this way, one bank may be selected, and then another while the first is still selected. However, this entirely synchronous solution degrades performance, since even if the enable signals become active, no selection can occur until the clock signal is available. Therefore, it would be desirable to maintain the performance benefits of asynchronous enable signals without resorting to dedicated enable signals for each memory bank.
Another solution has been to use an enable signal decoder for a minimum number of enable signals to select from among a larger number of memory banks. However, in this scheme, only one bank at a time may be selected. Therefore, it would be desirable to select multiple banks simultaneously.
Thus, a need exists for a way to reduce the number of enable signal inputs needed for memory bank selection and allow multiple simultaneous memory bank selection, while maintaining the performance benefits of asynchronous enable signals.